Title / Description
Code PRJ_PATH = /home/avers/work/tst TB_RTL = $(PRJ_PATH)/verif/verilog/tor_tb TOP_RTL = $(RTL)/Router_top_v3.2/Router_top_2D.v RTL = $(PRJ_PATH)/rtl SC_DIRS = . RTL_PPC = $(RTL)/ppc GLBL = /cad/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v RTL_DIRS = \ $(SC_DIRS) \ $(RTL)/Router_top_v3.2 \ $(RTL)/common_files_v3.2 \ $(RTL)/sram/sram_for_V5_fx70t_v3.2 \ $(RTL)/out_v3.2 \ $(RTL)/in \ $(RTL)/bui \ $(RTL)/pe_v3.2 \ $(RTL)/ni_v3.2 \ $(RTL)/vc_v3.2 \ $(RTL)/crossbar \ $(RTL)/midp_a \ $(RTL_PPC) \ $(TB_RTL) RTL_FILES = $(shell find $(RTL_DIRS) -maxdepth 1 -name "*.v") ppc_bram_elaborate_ver_files = $(wildcard $(addsuffix /*.v, $(RTL_PPC)/bram_elaborate)) ppc_bufs_m3_ver_files = $(wildcard $(addsuffix /*.v, $(RTL_PPC)/ppc_bufs_m3)) ppc_bufs_m3_vhdl_files = $(wildcard $(addsuffix /*.vhd, $(RTL_PPC)/ppc_bufs_m3)) PPC_LIB_ver_files = $(wildcard $(addsuffix /*.v, $(RTL_PPC))) PPC_LIB_vhdl_files = $(wildcard $(addsuffix /*.vhd, $(RTL_PPC))) ARCH_64BIT := $(shell uname -m | grep -c "64") ifeq ($(ARCH_64BIT),0) SC_PLATFORM := linux_gcc-4.1.2 MODELSIM_INI := /cad/Xilinx/simlib/EDK11.3_mti_se_linux/modelsim.ini endif
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1.1.2
1.1.2